In a typical integrated circuit (IC), multiple metal interconnect layers overlay the substrate and the circuit elements constructed thereon. The metal interconnect layers are separated from each other and from the substrate by dielectric layers. Each metal interconnect layer is formed into individual patterns of metal traces, or interconnects, that electrically connect the various circuit elements of the IC. Also, other circuit elements, such as capacitors, can be formed between the metal interconnect layers to relieve space constraints at the substrate level and to improve performance of these elements.
A common technique for forming the metal interconnects involves depositing a film of the metal material onto the top surface of the IC (typically a dielectric layer) and etching away the undesired areas of this film to form the pattern. This technique can also be used to form the capacitors between the metal interconnect layers.
Another way to form the metal interconnects involves etching the pattern into the dielectric layer to form trenches in the dielectric layer and then depositing the metal over the dielectric layer and into the trenches. The metal is then removed with a chemical mechanical polishing (CMP) or etching process back to the dielectric layer, leaving the metal in the trenches in the patterns of the metal interconnects. This second method is known as a “damascene process.” Via connections between the metal interconnect layers and the substrate structures may also be formed by damascene metallization processes. In fact, the via connections and the overlying metal interconnects can be formed in the same damascene process, called a “dual damascene” process.
Damascene metallization processes for forming the metal interconnect layers have gained in popularity over the metal deposition and etching types of processes described briefly above. The popularity is due in part to the fact that the CMP processes commonly used at the end of the damascene process create a fairly smooth surface upon which the next layers can be formed. The damascene processes can also avoid some of the complications of metal etching which have occurred as geometries of the structures (i.e. electrical elements and conductors) have been made smaller in width. For example, to construct metal elements or conductors of the same resistance or conductance as prior elements, but with a narrower width, the height must be made greater for a greater aspect ratio. To do so using metal etching processes requires that the metal be deposited in a relatively thick layer and then etched to form relatively tall and narrow structures with small gaps in between that are then filled with insulating material. It has proven very difficult, however, to use such techniques to form the tall, narrow, closely-spaced metal structures and then fill in the gaps. Damascene processes, on the other hand, have been proven to be able to form the necessary deep, narrow, closely-spaced trenches and to fill the trenches with the metal material to form the desired metal elements and conductors.
Due to the increasing popularity of damascene metallization, it has become desirable to form the capacitors between the metal interconnect layers using the damascene processes. The capacitor formation processes, however, are typically complex and require considerable extra steps to perform. Also, the capacitor structures formed thereby have complex patterns, which require stringent process controls.
It is with respect to these and other background considerations that the present invention has evolved.